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The 8051 Instruction Set

Atmel 8051 Microcontrollers Hardware Manual 1-50

4316E–8051–01/07

1.14.34 NOP

Function: No Operation

Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected.

Example: A low-going output pulse on bit 7 of Port 2 must last exactly 5 cycles. A simple SETB/CLR sequence generates

a one-cycle pulse, so four additional cycles must be inserted. This may be done (assuming no interrupts are

enabled) with the following instruction sequence,

CLR P2.7

NOP

SETB P2.7

Bytes: 1

Cycles: 1

Encoding: 0 0 0 0 0 0 0 0

Operation: NOP

(PC) ← (PC) + 1

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 115 116

Atmel 8051 Microcontrollers 1
Hardware Manual 1
Table of Contents 2
Section 1 3
1.2 Addressing 4
1.3 Arithmetic 6
1.4 Logical 7
1.5 Data Transfers 8
The 8051 Instruction Set 10
1.6 External RAM 11
1.7 Lookup Tables 11
1.8 Boolean 12
Instructions 12
C= bit1 XRL bit2 13
MOV C, bit1 13
JNB bit2, OVER 13
OVER: (continue) 13
1.9 Jump 14
1.10 Read-Modify 16
Write Instruction 16
Features 16
1.11 Instruction Set 17
1.12 Instructions That 21
Affect Flag 21
Settings 21
1.13 Instruction Table 22
1.14 Instruction Definitions 25
1.14.2 ADD A,<src-byte> 26
ADD A,direct 26
ADD A,@R 26
ADD A,#data 26
ADDC A,R 27
ADDC A,direct 27
ADDC A,@R 27
ADDC A,#data 27
1.14.4 AJMPaddr11 28
ANL A,R 29
ANL A,direct 29
ANL A,@R 29
1.14.6 ANLC,<src-bit> 30
ANL A,#data 30
ANL direct,A 30
ANL direct,#data 30
ANL C,bit 30
1.14.7 CJNE <dest 31
ANL C,/bit 31
CJNE A,direct,rel 31
CJNE A,#data,rel 32
,#data,rel 32
CJNE @R 32
,data,rel 32
1.14.8 CLR A 33
1.14.9 CLR bit 33
CLR bit 33
1.14.10 CPL A 34
1.14.11 CPL bit 34
CPL bit 34
1.14.12 DA A 35
1.14.13 DECbyte 36
DEC direct 36
1.14.14 DIVAB 37
DJNZ direct,rel 38
1.14.16 INC<byte> 39
INC direct 39
1.14.17 INC DPTR 40
1.14.18 JB blt,rel 40
1.14.19 JBC bit,rel 41
1.14.20 JC rel 41
1.14.21 JMP @A+DPTR 42
1.14.22 JNB bit,rel 42
1.14.23 JNC rel 43
1.14.24 JNZ rel 43
1.14.25 JZ rel 44
1.14.26 LCALLaddr16 44
1.14.27 LJMPaddr16 45
1.14.28 MOV <dest 45
MOV A,R 45
4316E–8051–01/07 46
1.14.30 MOV DPTR,#data16 49
1.14.31 MOVC A,@A+ 49
<base-reg> 49
1.14.32 MOVX <dest 50
MOVC A,@A+DPTR 50
MOVC A,@A+PC 50
MOVX A,@R 50
1.14.33 MUL AB 51
MOVX A,@DPTR 51
MOVX @DPTR,A 51
1.14.34 NOP 52
<src-byte> 53
ORL A,direct 53
ORL A,@R 53
1.14.35 ORL<dest-byte> 53
1.14.37 POP direct 56
1.14.38 PUSH direct 56
1.14.39 RET 57
1.14.40 RETI 57
1.14.41 RL A 58
1.14.42 RLC A 58
1.14.43 RR A 59
1.14.44 RRC A 59
1.14.45 SETB<bit> 60
1.14.46 SJMP rel 60
SETB bit 60
SUBB A,R 61
SUBB A,direct 61
SUBB A,@R 61
1.14.48 SWAP A 62
1.14.49 XCH A,<byte> 62
SUBB A,#data 62
XCH A,R 62
XCH A,direct 62
1.14.50 XCHD A,@R 63
XCH A,@R 63
1.14.51 XRL <dest 64
XRL A,R 64
XRL A,direct 64
XRL A,@R 64
XRL A,@#data 65
XRL direct,A 65
Section 2 66
Note: (*)For Timer 2 only 67
2.2 Special Function 68
Registers 68
2.3 Oscillator and 70
Clock Circuit 70
2.4 CPU Timing 71
2.5 Port Structures 73
2.6 Accessing 77
External Memory 77
2.7 PSEN 78
Reset Value = XXXX XX00b 80
Table 2-2. AUXR Register 80
2.9 Timer/Counters 81
2.10 Timer 0 82
2.11 Timer 1 84
2.12 Timer 2 89
Timer 2 Control Register 92
2.13 Serial Interface 94
Baud Rate Selection for 97
UART for Mode 1 and 3 97
Common Features Description 100
2.14 Framing Error 104
Detection 104
2.15 Automatic 105
Address 105
Recognition 105
UART Registers 108
Reset Value = 0000 0000b 110
Bit addressable 110
Table 2-24. T2CON Register 110
2.16 Interrupts 112
Regional Headquarters 116

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